It Has Been Stated Ã¢â‚¬å“judicial Review Is Concerned Not With the Decision but With the Decision-

Clark Marming · Monday, April 18, 2022

MCE
I�ƒ¢â�€š¬â�€ž¢m seeing quite a lot of misunderstanding the workings of MCE and then I�ƒ¢â�€š¬â�€ž¢m partly writing this to address it.
It is not the taboo that it has been fabricated up to become. There are iii options for information technology, namely Car, enabled and disabled.

Enabled only maxes out Power and electric current limits then that users don�ƒ¢â�€š¬â�€ž¢t accept to manually do these themselves.

Disabled sets these limits to intel�ƒ¢â�€š¬â�€ž¢s defaults. Even when you customize ratios, these limits are yet in identify unless manually adjusted.

Auto means that the board has liberty to decide what limits are reasonable, competitive, reliable and logical. Factors such as thermal, operation, Segment, competitor�ƒ¢â�€š¬â�€ž¢s out of box perf, stability are taken into account. Logical meaning that when you customize a ratio, all limits are raised to the max with the logical assumption that y'all want to run that frequency and not clip from power.
Therefore it is totally redundant to disable MCE and then max out power and current limits, since enabling MCE does the exact same thing and no more. Actually, simply exit MCE at auto if yous plan on overclocking, information technology does yous no harm.

TVB

Now for the current emphasis on totally stock perf of the i9�ƒ¢â�€š¬â�€ž¢s by the review sites, all the attending is on TDP only that�ƒ¢â�€š¬â�€ž¢south just a gnat compared to the camel swallowed. NO site actually talked about and examined the latest characteristic of the i9, Thermal Velocity Boost TVB. By default Intel enables this but I see that but Asus boards enable this at defaults. The other boards I tested have this disabled even at defaults.

What this does is it reduces voltage guardbands depending on core temp. Traditionally, the voltage request by the proc is always based on worst case scenario TJMAX, significant the voltage the proc thinks it needs for the frequency when temp is 100c. Information technology is well-known that the cooler the chip runs, the lesser the voltage needed. Therefore TVB is opportunistically reducing power and temps. The behavior is quite linear and I observed the post-obit on several samples.

TVB takes outcome from 40~50x on 99k and forty to 49x on 97k and xl to 47x on 96k, simply 40x to single core boost ratio. The V/temp curve runs from 0c to 100c. For example 150mv delta between 100c and 0c for 50x, meaning every 1C drop from 100c VID requested will reduce past one.5mv. The reduction is smaller as yous go down to 49x, the smaller the ratio the smaller the reduction, and beneath 40x you go no reduction. This is good for almost people running stock. You tin attempt this yourself by noting the VID idle, and then unplug your water pump and let the core temp rise slowly, noting down the correlated temp/VID, and see what i'm talking well-nigh.

During OC, when yous endeavor to run adaptive mode voltage with this mechanism, you will demand to change your perspective in how you lot ready the �ƒ¢â�€š¬�‹�"target adaptive voltage�ƒ¢â�€š¬â�€ž¢ since yous need to assume that�ƒ¢â�€š¬â�€ž¢south the voltage you become when 100c and practise the reduction to your lowest (commonly ambient) temp and gauge what voltage is needed to be set. So if y'all fix 1.35v for example, when you lot idle at 30c you volition become peradventure 1.25v instead. This tin can be confusing for many people, therefore nosotros disable TVB once you customize a ratio. This is non to say you cannot exploit this mechanism to work for you during OC merely you really need to find out your idle Vmin (lowest stable voltage). You can discover this option in CPU internal ability management in the bios and you can force it to enable during OC.
For those who want to check or try this on other boards, simply download r/w everything http://rweverything.com/ and add CPU MSR 0x150

Access this register and set chip 63 to 1 and [39:32] to 18h:

https://ibb.co/gUyvUf

Bit 3 shows you if TVB is enabled or disabled (0=disabled). If TVB is disabled, simply flip the bit and apply command 19 to write.

https://ibb.co/jCEDFL

https://ibb.co/muKDFL

Then you can come across what the default stock behavior is really like. This will truly impact temperature, ability consumption, boost frequencies when TDP is default, etc then those who want to dig deeper into �ƒ¢â�€š¬�‹�"stock performance�ƒ¢â�€š¬â�€ž¢ actually needs to get this correct.

The other thing that also affects �ƒ¢â�€š¬�‹�"stock performance�ƒ¢â�€š¬â�€ž¢ is the ACDC loadline programmed into the processor. Boards should permit CPU know the bodily loadline the lath is currently set to past writing the correct loadline. This doesn�ƒ¢â�€š¬â�€ž¢t mean that the board has to exist honest most information technology, and with the generous guardband Intel are used to providing (not every bit generous any more peradventure �ƒ¢â�€š¬â�‚��" well you lot know they demand to gene in stability later 10 years of heavy use for example), it is not uncommon for boards to prevarication to the processor so as to become it to undervolt. Yous cannot really tell how much the board has lied to the proc just at the aforementioned frequency/load, just past probing the inductor on unlike boards with a multimeter, yous can see that at to the lowest degree more than than one board is lying to the proc. Plain TVB setting should be similar during the test or else you get very skewed results every bit explained above.

Finally, VRM temp should not exist the only factor when evaluating a VRM, much less a whole board. For OC, my opinion is that transient response is very important. Contrary to popular belief, yous practice not need expensive equipment to test transient response. You can use Cache OC or AVX offset to exam this.

If you played with Cache OC, yous see that it is very intolerant of whatever undershoots. Straightaway y'all would hardlock or BSOD. You can even test it at default. Since information technology shares the same runway as cadre, set core ratio to something really depression like 40x. Ready min and max enshroud ratio to 43x and gear up a manual voltage like 1.15v. Run a heavy load like prime 95 not AVX. Dynamically slowly reduce the voltage 5mv at a fourth dimension. You volition find the VMIN this fashion. Once you lot detect the VMIN nether continuous load, stop prime95. If it doesn�ƒ¢â�€š¬â�€ž¢t hang, run it again, back and along betwixt running and stopping. Even try booting direct from bios with that VMIN. You will see that this VMIN requires a guardband for transient load changes, pregnant y'all volition need 5mv+++ more. You will observe bigger guardbands needed at higher cache. Manifestly the better the transient response, the guardband requirement is smaller.

There is also AVX offset, or ratio change mechanism in general that you lot tin can observe transient response. First, find the VMIN nether continuous heavy load like prime95 non AVX 26.6 on say 47x cpu ratio or something with a transmission manner voltage with AVX offset at 0.
Side by side set AVX outset to any value, such equally 1 or 2. Run the same frequency/load at it�ƒ¢â�€š¬â�€ž¢s VMIN. It will not last too long.

Avx offset or other ratio change mechanisms has e'er had this issue whereby voltage guardband needed is bigger
Heres why, the ratio modify takes identify past getting the core plls to go to sleep and and then waking upward to new pll frequency.
The transient is very bad and vehement when u run loftier loads cos it will become from actually loftier load to almost no load and dorsum to high load very quickly.

Now yous may think yous did not even run AVX. For AVX beginning, a lot of background stuff may run a few AVX instructions, such as dot net framework.
Sometimes u can encounter avx offset occur when u don�ƒ¢â�€š¬â�€ž¢t deliberately run avx, its usually very fast and you but see the small pockets.
Therefore the ratio change occurs quickly and vmin is raised due to the guardband requirement increasing.

The fashion to mitigate this is to use a steep LLC and higher vid. The transient will be better.

Yous tin can trigger this guardband by doing other stuff that changes ratio, such as when running prime 95, keep setting downwards short duration ability limit and upping it with XTU continuously.
The ratio will keep changing and finally hang when your guardband is just enough.
Or just keep irresolute ratio up and down.

Therefore utilise AVX first bearing the extra guardband in mind. This is totally the behavior of Intel�ƒ¢â�€š¬â�€ž¢south proc. Again, obviously you can judge the �ƒ¢â�€š¬�‹�"responsiveness�ƒ¢â�€š¬â�€ž¢ of a board by measuring the GB needed. For example you can logically conclude that a lath that requires 150mv GB is less �ƒ¢â�€š¬�‹�"agile�ƒ¢â�€š¬â�€ž¢ than a board that requires 80mv guardband.

Adaptive Voltage

Lets start from the basics, how the CPU'south Dynamic Freq volt scaling works.
#1 the mobo's bios tells the processor the electric current loadline characteristics via Ac DC loadline values.
#2 the cpu, based on its own native VF curve and the info in #1, requests for a voltage from the controller.
#iii the voltage that somewhen reaches the cpu is this voltage minus the droop from loadline

easier to empathise from an example:

10900k running at 4.9ghz currently and drawing 150A. bios programmed AC DC LL to 0.50MOhm.
the cpu's native vf point at four.9ghz is 1.30v.
the cpu anticipates 75mv droop. (V=I*R,,, 150*0.5) the cpu requests for ane.30v + 75mv = 1.375v from controller.
the electric current VRM loadline the user sets is level three which is about ane.1MOhm.
the actual voltage that the cpu somewhen gets after the vdroop from the mobo is 1.375v- (150*1.1)mv = one.21v

##Note: The above is an illustration without TVB voltage optimization enabled. if it is enabled, then information technology adds another variable into the equation @ #2 (volt requested for -volt optimization from temperature -> we leave this every bit nix so that it is more understandable in the above example)

Later agreement this, nosotros tin can improve explain Adaptive voltage, which is not also complicated just requires you to bear in mind the rules it follows.

ane) When cpu frequency is smaller than or equal to the highest default boost freq, for eg 5.3 on 10900k (lets call this p0 freq):
whatever yous set every bit an adaptive voltage is ignored by the cpu since it merely references its own native vf curve at freq <=p0freq

2) And even if you are at a freq college than p0 freq, if you set a value that is smaller than its native p0 freq vid, this gets ignored as well.

case:
10900k with a native vid of 1.5v at 53x. you run synch all cores 52x and try to set 1.45v adaptive. this is futile becos cpu ignores it due to 1)
then you go up to 54x and try to set ane.475v, this is futile as well as the cpu again ignores it due to 2).
and so you prepare voltage to 1.52v, so the cpu finally starts honoring this asking considering i) and 2) are faux.

=> so in short, adaptive voltage ONLY takes result if freq >p0freq & value > native p0vid. And fifty-fifty so the eventual voltage you lot become is the result later on going thru #1,#2,#3

so what to practise for freq <=p0 freq, how to get volt u want in this range? well, short of offsets / vf pt offsets, you can manipulate the variables in #1 and #3 to become the v you desire, ie manipulate AC DC LL values and/OR VRM Loadline values. for my preference, i would stick to a good VRM loadline that is good for transient, example Level 4, prepare it in this position and trim Air-conditioning DC LL values.

The svid behavior option just contains static AC DC LL presets, apart from "Trained" which is role of the AI algo, that sets a predicted AC DC LL value taking into account freq, cpu/cooler characteristics/vrm ll value.

South/w VID readings

South/west vid readings may non always reflect the actual vid requested from the controller, in fact, unless DC Loadline is written to 0.01, information technology wont.
what it reflects is really the voltage cpu anticipates to get, calculated from DC LL value.
so for example, when you lot meet VID reading of 1.35v and DC Loadline value is 0.5MOhm, what is really requested from the controller is:
(for simplicity im gonna leave out the stock-still 200mv offset requested past cpu for >=8cores)
1.35v+0.v*current at the moment:
for case:
one.35v + (0.v*180A) mv= one.44v

Then why dont we ready DC LL to 0.01 and AC LL to whatever we demand (since the actual vdroop compensation cpu requests for boils downward to AC LL Value)?
Well you lot can but when Air conditioning and DC LL values differ, the current and power calculations done by the cpu gets skewed.

New VF Pt offsets on Z490:

the vf bend refers to the stock vid of the proc at diverse freq and the vf pt get-go allows you to fine tune per each bespeak. All these pertain to adaptive voltage way instead of transmission mode, since manual fashion uses a fixed voltage setting across all freq. Bear in mind the nuance that it has to be monotonic and setting a higher freq with a lower resultant volt volition only get volt as low every bit the point earlier information technology.
As an example, you come across from bios carte or south/w that vf pt 53x is 1.334v vid
vf betoken 7 , the pt before that is 1.314v
say yous target 1.25v VID for 53x, setting negative offset of -0.084 for vf point 8(53x) volition but consequence in at actual 1.314v since vf point seven is 1.314v and u cannot set pt 8 lower than pt 7. at this time, you lot and then decide to prepare vf pt seven to negative -0.069â�‚�¬, and this sets vf pt seven downwards and also allows vf pt 8 to come up down to 1.25v.
the software tool i posted forces you to adhere to this rule so its useful for runtime testing in os and allows you to costless yourself from doing the math.

this is to illustrate the rule it adheres to, but an illogical approach considering i dont think 1 should target a voltage for a freq but target a freq and get the necessary volt for it.
so in actual use case, you would just exist trimming and trimming each point, double checking stability throughout the trimming procedure.

Edit: 11/nineteen

Update of new Feature: Overclocking TVB:

OverClocking TVB is an extension of the TVB feature allowing you to customize frequencies co-ordinate to temperature.
This, in my opinion, is a useful feature that milks the last bit y'all take got at low-cal loads without requiring additional voltage. In a nutshell, it takes that v~8C extra margin you've got, and converts it into additional frequency.
Information technology is simply supported on 10900K/non Thousand variants atm, and mayhap 10850K. IF unsupported, the information will display Northward/A
Everything TVB related is now grouped into the Thermal Velocity Boost menu:

At the meridian, it reads back the electric current configuration of the OCTVB.
For this to work properly, CStates must be enabled for proc to be active core aware! If you synch all cores, make sure you manually enable Cstates.
Active Cores refer to the row of settings applicable when that number of cores are active. Ratio Setting refers to the associated core ratio for that active core count. Temp A refers to Temperature A for that active cadre count above which the ratio would driblet by information technology's associated Ratio showtime. This offset is the Negative Ratio Commencement A pictured above. Temp B refers to Temperature B for that active core count above which the ratio would drop past a further 1x.
Let's take a simple example beneath:

Right now Cpu runs at 50C and simply core is currently agile. Ratio is therefore 55x.
User does something, the active core gets hotter and becomes 72C, and still merely one core agile. Ratio now becomes 55-i=54x because 72c is > Temp A 68C and the negative offet is 1. If negative starting time is 2 for eg, so it will become 55-two=53x.
And then, the user loads it further and now temperature is 82C. Ratio at present is 55-ane(from TempA) -one(from TempB) =53x because temp is > tempB of 78C and a further 1x is deducted. Temp B negative offset cannot be configured and is a stock-still 1x.
Then the user does something different and now 3 cores are agile. The applicable row becomes the third row in the picture above. CPU runs at 60C correct now and so none of TempA/B has been exceeded, therefore ratio is the original 53x. and so proc gets to 77C, TempA is breached, it's associated offset is 3x so proc drops to 50X. Again it runs hotter still, gets to 87C. TempB is breached, proc drops a further 1x and ratio is now 49x. And the story continues…

Hopefully, this instance is enough to explain.

The control is under Overclocking TVB, customize it using "Enabled"
When enabled, yous become to customize the params for each row (each agile core count) The Ratio, you lot configure information technology the main menu like you always practise, whether you go with synch all cores (if yous go with synch all cores pls manually enable cstates and then that the proc can tell number of active cores) or by core usage it doesn't affect this.

It can be very time consuming to customize it yourself, and so we have made two predicted presets for you, the +1boost profile and +2boost profile

Just use it ON Acme of your current/maximized oc setting.
It will do an additional 1x/2x on elevation of your electric current setting and gear up auto-calculated temperature boundaries based on the associated frequency. This does non add voltage considering it however uses the voltage before calculation the boost and merely tries to scrap some functioning from moments when there is thermal headroom.
So for case, I would load Ai optimized, and so enable to +1boost. I detect it stable, feel a bit adventurous, then I change it to +2boost and try.
Or my current OC is 54X @ one.4v, I continue this and I simply get into OCTVB to enable +1 boost. (if you go with synch all cores pls manually enable cstates and then that the proc can tell number of active cores, or only use by core usage and fix every cadre count to same value)

OCTVB for RKL is slightly different:
Guide:
https://www.dropbox.com/scl/fi/hz7la...cmorii2xv3k9zt

Menstruum Chart to visualize the decision-making process of the processor for Voltage and Frequency. Plain the evaluation is continuously looping and the 5 and F flows are intertwined, ie yous can imagine the Frequency flow continues into the voltage menstruum. Not exactly and then, just shut enough for comprehension.